Huge on-chip eDRAM L3. – 6x latency improvement. – No off-chip signaling rqmt. – 8x bandwidth improvement. – 3x less area than SRAM. – 5x less energy than. In a previous Power8 article, the performance and scaling benefits of IBM’s eDRAM capability were mentioned. One thing that should be stated. IBM Corp. took another step toward embedded DRAM and away from SRAM at ISSCC this week, pushing eDRAM as the technology to take over the SRAM.

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June 18, at Fab Equipment Challenges For Logic is strong, memory is weak, and uncertainty in China could affect demand. Memories play a […]. Figure 2 shows a layout diagram for the companion Centaur memory buffer chip. Figure 3 also shows a picture of the metal-insulator-metal MIM structure of the capacitor for the bit cell. There, the fin switches from mono-Si to poly-Si which iibm the connection to the DT capacitor. With software multi-threaded heavy workloads, where the data in the cache will be accessed simultaneously by multiple cores and hardware strands, eDRAM may suffer in comparison to multi-ported SDRAM due to excessive inefficient re-loads from main memory and inefficient sharing.

This name will be displayed publicly. Experts at the Table, Part 1: In this 14nm process IBM switched to a FinFET from a planar transistor which introduces a new sdram of challenges since they now have to connect to a thin fin meaning the strap size is also reduced meaning resistivity becomes a more profound problem.


I would expect that engineers tuned Ibj for the Database market. The discourse on possible trade-offs have been silent, which confuses me from the media. The entire process described leads to the final product — the deep trench embedded DRAM. Spelling error report The following text will be sent to our editors: The poly with all the other layers go up to and into the BOx but stay fully within the BOx. One thing that is immediately noticeable is that the eDRAM is sitting alone in its own chip.

Memories play a big role. More Than a Core Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

Since this eliminates the need for the sidewall nitride spacer they have always used previously in order to protect the BOx during the interim processes, this change effectively managed to extract additional density from the denser packing of the trenches.

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November 11, 1 Comment. Power Delivery Affecting Performance At 7nm Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.

Semiconductor Engineering The Power Of eDRAM

December 25, 17 Comments. Finally a liner is applied after which the trench is filled with the sdram probably arsenic-doped silica glass ASGn-type polycrystalline silicon. Managing tens of thousands of devices with hundreds of thousands of managed resources often requires thousands of threads in a single process with very regular minute polling intervals required tremendous throughput.


Strange physics and future devices. There are also a lot of other factors that come into play when evaluating DRAM, such as performance and data retention, but this at least provides a edrxm high-level comparison.

Connection to Network Management Network Management traditionally deals with extremely highly threaded workloads.

iibm You then remove the hardmask and a thin high-k dielectric like HfO 2 is deposited and grown in the trench. With multi-process heavy workloads, where data in the cache may not be simultaneously accessed from different cores or ibk strands, eDRAM may be a good fit.

Power is not a substantial player in the Network Management world, so I would not really expect engineers to tune the CPU for this type of workload.

Hybrid Memory Ed Sperling. The Deep trench extends through the top silicon, through the oxide layer and into the base substrate.

The Power Of eDRAM

This decision cost the cache a few cycles of latency. AMD has the volume to use this tech. Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.